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Design And Verification Of Instruction Fetch And Dispatch Unit In Hign Performance DSP

Posted on:2016-11-10Degree:MasterType:Thesis
Country:ChinaCandidate:J PengFull Text:PDF
GTID:2348330509960933Subject:Software engineering
Abstract/Summary:PDF Full Text Request
As the constantly development of computer and IC technology,DSP come into being and develop fast,now it has been widely used,promote the national information technology and brought huge effect on national development and people's life.DSP technology had been becoming maturer and maturer from its born at TI company.Today the number of multi-core high performance DSP which supports SIMD and parallel dispatch increase higher and higher, core architecture and design also become the key of improving speed and data manage ability of DSP.The thesis made a design and verification of instruction Fetch and Dispatch unit based on a high performance 32 bits DSP chip which adopt VLIW and 16/32 parallel dispatch supported,among it,we have presented some important technology including instruction prefetch,instruction buffer queue and boundary-across dispatch which deeply affect on DSP frequency and code density.Actually below innovation and work have been finished:(1)Propose a design method and requirement of Fetch and Dispatch Unit according to the whole structure of FT-MX and instruction set,and analysis their main function based on core structure and pipeline.(2)The design of dispatch unit,including boundary-cross instruction dispatch,fetch from L1 P,also support the write and read of emulation test unit.(3)The design of instruction instruction fetch unit,including pipeline fill,branch address buffer, product of address and invalid,besides,the thesis also gives the agreement between instruction fetch and other units in core,it has a important effect on pipeline running.(4)Give a design compile for Fetch and Dispatch unit under the tool of synopsys company and analysis its result which is benefit for optimization.(5)Build the verification bench for the system functional verification of instruction fetch and dispatch,and build functional model according to the RTL design of unit,then make a assertion and equal check about instruction fetch and dispatch unit which has improve the integrity of verification effective.
Keywords/Search Tags:DSP, Flexible Instruction Set, Instruction Fetch, Instruction Dispatch, Pipeline technology, System Verification, Assertion
PDF Full Text Request
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