The Research Of New Anti-SEU Memory Read-Write Structure And ECC Encoding Method

ECC(Error Checking and Correcting) technique is an important method to solve the SEU(Single Event Upset) problem of SRAM. An ECC block, which uses the improved hamming encoding and decoding algorithm and introduces a new anti-SEU memory read-write structure, is designed to reinforce the SRAM memory considering the anti-SEU performance, the redundancy memory capacity and system read-write efficiency. In order to prevent the ECC block from affecting the SRAM memory read-write operation, the ECC block is introduced to the memory and controller interconnection bus in parallel; The memory space is divided by 512 bytes and every 512 bytes is encoded using improved hamming algorithm which generates 3 Bytes checking and correcting codes; The RTL level ECC block is designed using Verilog HDL, whose scale is 15 thousand gates (including 1K flip-flops) after it is synthesized, and the frequency is up to 80MHz. Hardware Validation is processed using the FPGA EP2S60F1020C3 of ALTERA StratixⅡfamily, which proves the ECC encoding and decoding module fulfills the design requirement.