Research Of Evaluation System Of Ecc-based SRAM Harded Technology

With the development of integrated circuit fabrication processes, the feature size of circuit is decreasing. When the radiation such as high energy heavy ions and other particles hit the sensitive position of semiconductor devices, the charge can be deposited. It can cause an single event upset effect[1]. SEU(Single Error Correct) currently becomes the main factors, which cause SE(Soft Error) of SRAM(Static RAM). It significantly reduces the reliability of SRAM under radiation environment. Therefore, the reinforcement of SRAM becomes one of the key research field of anti-radiation in space. In SRAM hardened design, ECC(Error Correcting Code) is an effective solution to anti-SEUs. In order to avoid the ECC-based SRAM reinforcement scheme that can not achieve the expected demand or produce a lot of redundant circuits to achieve the expected demand, an evaluation system must be needed. But at home and abroad, evaluation of ECC-based SRAM reinforcement system is not fully mature, there is no uniform standard. So a scientific evaluation system of ECC-based SRAM reinforcement must be neededThe mainly idea of this thesis is to establish a system that can be used to evaluate the ECC-based SRAM reinforcement. Assessment model use MTTF(Mean Time To Failure) that is the most widely used measure of the reliability parameters to evaluate the reliability of ECC-based SRAM reinforcement.Assessment system of this thesis is divided into two parts. One is a mathematical model to evaluate reinforcement system and the other is FPGA testing system that is used to test the complete reinforcement structure. The two-part of system are designed for the evaluation of ECC-based SRAM reinforcement. Two parts of the system constitute a complete evaluation system. The main feature of the two parts is below.(1) Mathematical model to evaluateBased on the Characteristics(error pattern characteristic and error overlapping characteristic) that is summarized in this thesis, this thesis combines with the idea that approximately equal SRAM that occur MBUs(Multi-Bit Upset)[2] to SRAM that only occur SEUs(Single Event Upset), to establish an assessment models. The calculation system is very simple, and speed is very fast.(2) FPGA test sectionThe research presents a testing platform that combine with FPGA and upper computer. On the basis of the SEU characteristic that is summarized by this paper, We use PC configure space environment variables to the FPGA testing platform, then FPGA platform can test the reinforcement model and statistically calculations the reliability parameter MTTF. The test platform mainly rely on FPGA hardware circuit, it has high speed, high design flexibility, and scalability characteristics. As opposed to the mathematical model, it has high statistical accuracy, scalability and other features.