CDV Verification Of A 2.5G Bandwidth Optical Transport Network Chip

With the constantly increasing design scale, the average gate count for chip designs has already exceeded one million, while the verification has become one of the main bottlenecks in the designing process. Currently by virtue of its speedy performance, simple modification, perceptual intuition and high efficiency, CDV verification has been more and more popular with verification engineers.Based on the methodology of CDV verification, this paper mainly carries out a verification study on Optical Transport Network (OTN) chip in combination with the R&D project. This chip is widely used in the transport device with the operation frequency of 155MHz. It is designed with the 90nm technology of the IBM and contains about 30 million gates. It mainly processes the mapping of client signals into OTU1, and the demapping of client signals out of OTU1, at the same time, monitors the overheads extracted from the operation and inserts the changed overheads into the operation. In order to verify this chip, a high-efficiency automatic platform is established, which provides an interface connecting the DUT with the platform properly. It can generate highly pertinent vector in high level, and support the verifications based on RTL and assertion. The verification of client mapping to wave is operated on that platform, and eventually, the function coverage could reach up to 100%. Combining the verification practice, this paper has discussed some important parts of the verification process in detail and summarized the entire CDV verification flow which could play a significant role in the verification of other chips for reference.The successful completion of this multi-million gate ASIC in this paper not only provides theoretic evidence for CDV verification, but also has a great referential significance in idea and method for the verification study of other chips.