| In accordance with the aggressive scaling of the Metal-Oxide-Semiconductor-Field-Effect-Transistors (MOSFET), the gate oxide thickness has been getting thinner in each new generation over the past 3 decades. There exist a number of problems for the continued scaling of ultra-thin silicon oxides much below 3nm, the major one being the large direct tunneling leakage current. The first portion of this thesis covers various aspects of the tunneling leakage current in ultra-thin oxides, including the basic theory of tunneling in MOS devices, the modeling of tunneling leakage current in ultra-thin oxides, and the behavior of tunneling current in dual-gate CMOSFETs. The scaling limit of silicon oxide is projected based on both theoretical calculations and experimental results.The second portion of this thesis is dedicated to the development of a viable alternative gate dielectric to thermal oxide for future generations of devices. In particular, high-quality silicon nitride films have been successfully synthesized by a novel Jet-Vapor-Deposition (JVD) technique. The JVD technique utilizes a high-speed jet of light carrier gas to transport depositing species. Directly deposited on Si at room temperature, the JVD nitride exhibits many excellent properties, including low density of interface traps as well as bulk traps, low trap generation rate, high breakdown strength, and strong boron penetration resistance. The most attractive property for gate dielectric application derives from the higher dielectric constant of silicon nitride, which allows the use of a physically thicker film to achieve the same device performance, but with substantially reduced tunneling leakage current, thus extending the gate dielectric scaling limit. The carrier transport mechanisms in JVD nitride and their implications in gate dielectric scaling have also been studied in great detail.In addition to the JVD silicon nitride, nitride/oxide (N/O) stacks produced by an in-situ JVD deposition process have also been studied. The JVD-N/O stack not only shows excellent interface properties, but also suppresses the excessive low-field leakage current in the single nitride layer. It is a trade-off between the pure silicon oxide and the pure silicon nitride, and may be considered as another candidate to serve as an advanced gate dielectric, especially in the 2--3 nm thickness regime. |
