Investigation of plasma implantation and gate oxide charging during plasma processing

Plasma Immersion Ion Implantation (PIII) is an alternative to conventional implantation for high dose and low cost applications. Full commercialization of PIII requires process models for understanding the effects of the implant parameters on the final implant profile. A model is developed that predicts charging damage for all plasma processes, including PIII.;The basic coupled plasma model for PIII contains three separate modules, the plasma, the wafer structure, and the substrate bias. The plasma module consists of a set of physically derived equations from a Quasi-Static Child Law analysis for the sheath expansion and plasma currents. The wafer structure module accounts for the type of devices and the presence of thin gate oxides on the wafer at the time of the plasma process. The substrate bias drives the implant, and hence, the effects of its characteristics on the plasma process is studied.;Implant energy profiles are generated with the coupled PIII plasma model. A pulsed PIII implant is not mono-energetic, but rather contains a significant energy spread. The contribution of the rise time of the implantation pulse to the energy spread is minimized by reducing the rise time as close to zero as possible.;The basic PIII plasma model has been extended to take into account dielectric substrates, multiple plasma ion species, and ion sheath collisions. The extended model allows optimization of the pulse width, pulse frequency, bias voltage, and plasma ion density to control substrate charging while maintaining an acceptable dose rate.;The issue of gate oxide scaling and charging damage has been resolved through the development of a Universal Charging Damage Model. A load line analysis of the plasma impedance and gate conduction establishes the stress condition during the plasma process, and an oxide reliability model correlates the stress condition with oxide damage.;Assuming identical plasma conditions during processing, there are three stressing regimes observed with oxide scaling. Thicker oxides undergo constant voltage stressing, while thinner oxides undergo constant current stressing. Ultra-thin oxides, thinner than about 3 nm, also undergo constant current stressing, but the electrons tunnel by direct tunneling rather than Fowler Nordheim tunneling.;Combining both the Coupled Plasma Model and the Universal Charging Damage Model allows the prediction of charging damage for PIII. Simulations predict that the amount of damage depends on the frequency of pulsing. Device circuit structures and parameters, such as wells, channel doping, circuit antennas, and dielectric substrates affect PIII charging damage. Simulations show that devices on dielectric or SOI substrates are generally immune to gate oxide charging damage during PIII.;The addition of the dielectric, multiple species, and collision modules to the plasma, wafer structure, and bias models forms a fairly comprehensive one dimensional PIII dose and implant simulator. The Universal Charging Damage load line analysis forms the framework for analyzing plasma induced charging damage for all plasma processes. (Abstract shortened by UMI.)...