DFM Based Research And Test Chip Design

As the integrate circuit (IC) comes into very deep Sub-micron era, some new technology have used in semiconductor manufacture process, such as Sub-wavelength Lithography, copper electroplating, chemical mechanical polishing and so on. Although those new technologies have develop the IC technology, its took into lots of new defects. Those defects influence electrical functionality and performance of IC products and lower the production yield. Especially on Sub-micron era, some defects which were neglected in past could made the chip terrible failure.This dissertation tries to investigate some kinds of problems of IC manufacturability and yield by studying CMP process and test chip. The flow of IC design and manufacture is described at first. Then some types of yield loss such as Optical Proximity Effect (OPC), Chemical Mechanical Polishing, random defect, system defect and so on. As for the CMP process, which are serious impacting yield outcome in today's nanometer IC designs are analyzed. Then, we have studied the design for manufacturability problems by the design of test chip, which can extract resistance and capacitance of test structure at the same time. This test chip have saved the chip area and let the extract data more accuracy. At last, by the study of CMP and test chip, we concluded our work and summarized the future work.