Chemical Mechanical Polishing (cmp) Impact On The Electrical Characteristics Of Analysis And Optimization

With the developing of modern very large scale integration (VLSI), interconnect is playing a more and more significant role in the timing of digital VLSI systems. In the design of system-on-chip (SOC), the demand of capability and power consumption are increasing. With the scaling of semiconductor technology, some techniques have changed, such as optical proximity correction (OPC), chemical mechanical polishing (CMP). During CMP process, the metal thickness variation because of the asymmetry of metal density brings about dishing and erosion. In the process of multi-layers producing, density such dishing and erosion have a little effect on first or second layer, but in the higher layer, because of superimposition of such dishing and erosion, short circuit or open circuit that we do not expect may happen, then affect the whole circuit. So, the dummy fill is needed to equalize the spatial density of the metal and improve the flatness of metal surface. But in the another hand, dummy metal fill has a strong interconnect coupling capacitance, resistance, signal delay and power consumption.The purpose of studying the dummy fill is to decrease the value of such parameters and achieve minimum performance degradation. We hope to achieve minimum performance degradation while the required planarity is kept, so that multi-layers can be produced while the cost can be reduced, and the yield and economic benefits improved. This paper deals with the influence of the dummy fill. It is hoped to find out the key factor:the shape, area, location or the parallelism border between dummy fill and interconnect. This paper discusses the flatness improvement, puts forward a series of strategies, reduces the coupling capacitance increased by the dummy fill and optimize the flatness and electricity performance.