Research On Chemical-Mechanical Polishing Yield Driven Routing Algorithm

As VLSI technology advances into the nanometer regime, the manufacturability and the yield of chip have become key issues for IC design and fabrication. CMP (Chemical-Mechanical Polishing) is one of the factors that influence chip yield. Routing is an effective stage for dealing with these issues. CMP yield driven routing algorithms are investigated systematically in this thesis, which are performed during early routing, interconnect optimization and post processing respectively. The main contributions are as follows:1. A Cu CMP Yield driven full-chip routing system is proposed. This router introduces Cu ECP (Electroplating) and CMP models, and integrates feature density driven global routing, feature density driven layer assignment and weight density driven detailed routing in it. This can lead to a uniform wire density distribution in each area on each metal layer for reducing CMP topology variation effectively. Experiments show that the proposed algorithm can reduce 6%-7% post-ECP variation and 15%-17% post-CMP variation on average than CMP-aware detailed routing algorithm. Furthermore, it can insert smaller amount (about 5%) of dummy fill, which means less impact on performance.2. CMP influences circuit performance in two ways: ILD (interlevel Dielectric) thickness variation and dummy fill for CMP. Two CMP aware buffer insertion algorithms are proposed in this thesis to improve the accuracy of interconnect optimization during routing. The former calculates the ILD variation after CMP via a systematic ILD model, and the latter presents an effective dummy fill estimation model after layer assignment to consider the impact of CMP on buffer insertion during routing. Experimental results verify the necessity of considering ILD variation and dummy fill during early design, and the proposed CMP aware buffer insertion algorithms are effective. 3. Dummy fill insertion during post-routing for CMP enhances the planarization of wafer surface. However, it causes significantly varying impact on the circuit performance. A performance aware dummy fill insertion algorithm is proposed. Critical nets are considered and fill regions are classified according to the criticality of the surrounding nets. Analytical hourglass-shape fill patterns are inserted in each fill region. Experimental results show that the proposed algorithm can reduce the delay of net by 15% on average than the traditional algorithm.