The Design And Implementation Of FIR Filter Using FPGA

With the rapid progress of IC industry,the capacity of the FPGA is becoming larger and larger.It enables the implement of the system on a programmable chip(SOPC) is possible.SOPC design methodology is the product of the Computer Aided Design(CAD),Electronic Design Automatic(EDA),and Large Scale Integration(LSI).It 's goal is to integrate more electronic system in a FPGA chip, including CPU,interface logic,coprocessor,accelerate system,DSP system,digital communication system,memory.Using the SOPC,it could make our product more integrated,credibility,steadily,smaller volume,power consumer and time-to-market,and the cost.This paper introduced the basic knowledge of FIR digital filter firstly,outlined the FPGA design methods and processes,introduced the whole flows of designing the developing board,including the concept of SOPC;the environments and processes of designing both hardware and software,the system level design of the developing board;the protraction of the schematic and the PCB layout;debugging each component and loading the system to the FPGA chip.At last,an example of implementing a FIR Filter on the FPGA board was given to demonstrate the flows of the Digit Signal Process(DSP) on developing board.Simulating experiments,both on software and hardware,also have proved the efficiency of method,So design of Digital Signal Processor Based on DSP Builder accelerated dramatically。...