| Automatic face recognition has great potential applications in public security, intelligent surveillance, digital personal identity, electronic commerce, multimedia, digital entertainment, etc. Over the past 30 years, great progress has been made in face recognition, but how to reduce the time consumption is still a great challenge.In this paper, we design an embedded structure to achieve the face recognition system, which is suitable for real-time processing and more portable. Currently there are two solutions in digital signal processing field - DSP and FPGA. This article compares the time consumption and chip resources consumption between FPGA and DSP, then introduces a way to make FPGA and DSP work together in AFR algorithm.As one of the main research of the key scientific and technological project of Shanghai in 2007—"Nakedness-Eye Stereoscopic Display Based on Single Chip DMD" under the project grant number 075115002, this paper starts from the key issues of the embedded face recognition system, studys the principle of parallel algorithms, face detecting, the traditional AFR algorithms, the cooperation of DSP and FPGA, the conversion from serial algorithms to parallel algorithms, the hardware design for the whole system and so on. Finally, our design is proved to be effective through the comparison of experimental result and the experimental data from other bibliographys. In this paper our main work is as follows:1. We propose parallel computing methods to solve matrix calculation, multiple convolution operation and other high complexity algorithms in face recognition system.2. We design the architecture of DSP + FPGA for high speed embedded face recognition processing.3. This paper divides AFR algorithms into two parts, one is suitable for serial processing, and the other is for parallel processing.4. We fabricate PCB boards and write software to implement the system function. The experiment is done to verify the validity of the method this paper proposed. |
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