Low Power Ultra High Speed CMOS Adder

The blooming development of Computer Science has led to the growth of integrated circuit (IC) devices. Most of the Very Large Scale IC (VLSI) applications, such as digital-signal processing and microprocessors, use arithmetic operations extensively. In addition, among these widely used operations, subtraction and multiplication are most commonly applied. The 1-bit full adder is the building block of these operation modules. Therefore, enhancing its performance is crucial to meliorating the performance of overall modules. Meanwhile, as the widespread use of portable IC devices, such as MP3 players, mobile phones and PDAs etc., IC engineers are required to improve the performance of existing operation modules in some aspects, especially in power depletion and size.Adder is the basic component of arithmetic operations in microprocessor. Usually, the operations in many kinds of microprocessor, DSP devices, and digital circuits are implemented by adders in binary system. For instance, subtraction can be realized by addition of complements, multiplication can be achieved by using successive addition, division can be implemented by successive subtraction and comparison operation can also be brought about by subtraction. Obviously, high speed, low power adders with high performance play an important role in microprocessors.Four novel types of low power adder cells are proposed in this thesis. All Simulations are implemented using Cadence Tools in 180nm CMOS process technology with a 1.8V supply voltage. The simulation results show that they can achieve the design requirement of low power, high speed, and small Power-Delay product. In Chapter 5, the author also presents a 2 bit dynamic high speed and low power adder. The simulation result proves that it achieves the goal of low power and high speed. In the end, further discussion of other adders such as"Tertiary-tree Adder"which can improve the performance of VLSI, especially in low power and high speed is provided.