Parallel Feedback Adder Study

Adder is one of the most important computing devices in digital computer systems. Besides its explicit arithmetic (such as addition, subtraction, multiplication, and division) performed in a program, adder is also used to increase the value of program counters and calculate effective addresses. This paper further studies a new theory of adder and its basic structure. The new adder is an asynchronous adder whose basic unit is half adder, called Parallel Feedback Carry Adder (PFCA) as its carry mode is parallel feedback. In theory, compared to the adders (e.g. RCA, CLA, CSeA, CCSA) based on full adders, PFCA is faster in speed and smaller in area. Two hardware implementations are proposed to verify the new design theory in this paper and they are implementations in FPGA and with CMOS gates. PFCA is implemented in Vertex 4 of Xilinx and simulated in Modsim, whose results show that there are two disadvantages:limited bit length of PFCA and worse performance. While the bit length can reach any bits when PFCA is implemented with CMOS gates. HSPICE simulation results show that PFCA has obvious advantage over RCA, CLA, CSeA and CCSA in speed and area. As complementary part of performance, reliability mainly measured by confidence level has analyzed in this paper. An advanced structure of PFCA is proposed to eliminate the timing hazards and to enforce the reliability of PFCA. The new structure not only maintains the advantage of PFCA, but also eliminates the timing hazards. Generally, PFCA shows potential applications especially when bit length is longer.