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FPGA Prototype Design Of MPEG-4 AAC Audio Decoder

Posted on:2010-06-23Degree:MasterType:Thesis
Country:ChinaCandidate:B L WangFull Text:PDF
GTID:2178360275477888Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Compared with other music formats for commercial use in the digital audio compression field,MPEG-4 AAC is outstanding with better audio quality,higher compression rates,more channels and variety of sampling rates,and it's the only advanced broadcast audio format confirmed by European Broadcast Union by now.In this essay,the system architecture is firstly established;then,considering the factors such as speed and area,the FPGA prototype is designed and the function is validated;at last,in the technology of 0018um,MPEG-4 AAC decoder is implemented in ASIC.The contribution of the essay is summered as followed:(1).Two systematical designs for different specified goals are brought forward,and compared with the common architecture.The decoder can meet the real-time requirement with much redundance for the audio less than 2 channels,so one systematical design for smaller area is given with lower speed;as for the audio with multiple channels,systematical design for higher speed is necessary,at the price of bigger area.(2).An FPGA prototype chip design of MPEG-4 AAC audio decoder is implemented.In bit-stream decoder module,a shift register architecture with configurable bits and automatic laoding is proposed;in noiseless decoder,the parallel algorithm for Huffman decoding is chosen after comparing with other two algorithms on speed and memory capacity;in re-quantization module,a algorithm of div-8 look-up-table is used among all kinds of look-up-table algorithm by balancing the value of SNR and resource of memory.The FPGA prototype cost 20929 ALUT, 14771 registers,and 2,737,480 bits memory on Stratixâ…ˇEP2S180.And the experiment results show that prototype can play AAC music with good quality.(3).Finally,MPEG-4 AAC decoder is implemented in ASIC in the technology of 0.18um,After synthesis using DC Compiler and STA(Static Timing Analyze)using Prime Time,a frequency of 50 MHz is achieved.And after place&route using Astro,a layout of MPEG4-AAC decoder chip with 17.27125 mm~2 is finished.
Keywords/Search Tags:AAC audio decoder, ASIC design, systematic design, RTL design
PDF Full Text Request
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