| With the rapid development of communications, speech communication is very important and indispensable in modern commuication systerms. ITU-T has also put forward a series of standards in low rate speech coder and decoder,including recommendation G.723.1. Many design of G.723.1 coder and decoder are implemented by the DSP. But because the DSP cost is so high, it limites the utility of G.723.1 decoder. Using ASIC to design G.723.1 decoder can reduces the cost, in order to let it be used in more domains.At first, background of task, intention and development of the speech coder have been introduced. Then this paper briefly recounts the principle in low rate speech coder, researchs speech decoder of G.723.1 and focuses on design the framework of the G.723.1's decoder.This paper implements the arithmetic function of G.723.1 decoder by an embedded DSP software core. The code of the G.723.1 decoder has been designed, converted into binary code and stored in the ROM. The design flow of G.723.1 decoder has been analyzed in detail. Also the function of every module has been described. To make the code efficient, the program of G.723.1 decoder has been optimized and debugged. The debugging result indicates that the output of speech decoder is satisfied in nature degree and differentiability.At last, ASIC design of G723.1 decoder has been accomplished, and modules of I/O interface have been desgined by using hardware description language Verilog. To achieve a correct result, the RTL simulation and synthesis have also been performed. The synthesis result of whole decoder's circuirt is 16124 gates. |
