Behavioral Simulation For Design Optimization And Noise Performance Estimation Of Phase-Locked Loops

In a design team, when designing a PLL, one designer often concerns oneself with one or several blocks design. So it is important to check the design by simulating the blocks, which is the most often works to do during a design. Now there are some useful and powerful simulators which can simulate and verificate the digital design. In analog design, HSPICE and Spectre are the prevalent simulators. But none of these simulators can doing mixed-signal simulation perfectely.Phase-locked loops (PLLs) are used to implement a variety of timing related functions, such as frequency synthesis, clock and data recovery, and clock de-skewing. Any jitter or phase noise in the output of the PLL used in these applications generally degrades the performance margins of the system in which it resides and so is of great concern to the designers of such systems. Jitter and phase noise are different ways of referring to an undesired variation in the timing of events at the output of the PLL. They are difficult to predict with traditional circuit simulators because the PLL generates repetitive switching events as an essential part of its operation, and the noise performance must be evaluated in the presence of this large-signal behavior. SPICE is useless in this situation as it can only predict the noise in circuits that have a quiescent operating point. In PLLs the operating point is at best periodic, and is sometimes chaotic.The motivation of this thesis is to propose a methodology of behavioral simulation for design optimization and noise performance predicting of PLLs. The idea in this thesis is modeling the blocks of a PLL with Verilog-A, which is a behavioral HDL. So we can perform mixed-signal simulation by this method. We also can predict the jitter of the PLL and can find out the nonideal effect inside the special block by co-simulation, which means doing a simulation when some blocks in SPICE netlists and others in Verilog-A or some in Verilog-A and others in verilog coding.The samples in this paper prove the method is effective and can shorten the simulation time, improve the design efficiency evidently.