The Design Of Universal Asynchronous Receiver Transmitter Based On FPGA

Universal Asynchronous Receiver Transmitter(UART) is a serial communication interface which can support short distance and long distance data transmission simultaneously,it is widely applied to data exchange between a microcomputer and peripherals.Such as 8251,NS8250 and NS16550 are commonly used UART chips,but the disadvantage of these specialized serial interface chips is transmitting data relatively slow.Therefore,they can't be used in high-speed data transmission.The more important is that they are non-portable,which certainly will increase the complexity of interfacial link,and decrease stability and validity of the whole system when these chips are used to process the communication between PC machine and FPGA chips.According to the characteristics of the UART and the portability advantage of FPGA designs,this paper puts forward an embedded UART design method based on FPGA chips.The design method includes description form of FSM and design approach of Top-Down.It's good to take advantage of VHDL to program the slave module and top module of UART,and then integrate them into the interior of FPGA chip.In this case it improves not only the disadvantage of the traditional UART chips but also makes the whole system more compact and more reliable.The UART of this paper supports standard RS-232C transport protocol.The main of the design includes transmitter module,receiver module,line control and interrupt arbitration module,modem control module and two independent data buffer FIFO module.On this paper,the UART design has variable baud rate,the length of data frame and odd-even checking mode.Moreover,it has interrupt source,interrupt priority level and the ability of anti-interference and self checking.Additionally,it also can fulfill duplex communication for the separate transmitter data buffer and receiver data buffer.Besides these features,the most important is using the IP multiplex technique to design the data buffer FIFO and adopting two selectable data buffer mode.In this way, it can not only support the low speed data transmission but also the high speed data transmission.Therefore,it can achieve the maximization of the resource utilization.During the concrete course of the design,first to synthesize and optimize and then simulate and verify,at last download and implement each functional module via the Synplify Pro,Models-im facility and the integrate software development environment of the ISE.Every result declares that the UART designed in this paper reached the demand of expected design goals.