The Design Of Image Acquisition And Preprocessing System Based On FPGA

With the development of automobile industry,it favors people with facilities, meanwhile,it also has brought greater pressure to the traffic.Due to its more and more obvious harm,the issue of automotive saftey becomes the focus question that people pay attention to gradually.This thesis as part of the vision-based automatic collision avoidance system,including the image acquisition and pre-processing,is very important in resolving the issue of automobile safety.This thesis has compared the computer,the digital signal processor,the ASIC and FPGA in the real-time application of embedded system,analyzed the advantages of the FPGA used to process images to resolve the problem of real-time,studied the features of FPGA,including design flexibility,programmability of software and hardware,good integration and so on,analyzed the design process and development environment in the FPGA.Combined with the feature of large amount of data in the real-time image processing,we decided to choose FPGA as the core component in this system.This system comprises image acquisition,image storage,image processing and real-time displaying function modules.The acquisition of digital image front end uses a CCD image sensor to collect the real-time image,and the output analog signal of the sensor is converted into digital signal by SAA7113.Then FPGA extracts effective luminance signal from the digital signal.The image storage module uses a 32MB SDRAM to store the considerable digital data.We design a simple SDRAM controller in FPGA to interface with SDRAM,its main tasks are initialization,periodic refreshing,continuous reading and writing.In image processing module,we design hardware circuits for median filtering and edge detection.The pipelined processing methods are used in circuit design to raise processing speed.The real time display module sends the signal after processed to the DA chip and generates the VGA timing. We can use a VGA monitor to observe the effect of image processing real-timely.In addition,we generate a NiosⅡkernel and some relative modules in FPGA, including two PIOs and a Flash controller.The PIOs are used to simulate theⅠ~2C timing to configure SAA7113,the Flash controller is used to interface with the Flash chip.This thesis emphatically researches of the hardware design and the interface module.In hardware design,parts selection and PCB design are difficult points;In interface modules,Image acquisition and image storage are difficult points.In this thesis,we pay more attention to hardware implementation of the image processing algorithm than the algorithm itself.At present,The hardware and software of the system have been successfully debugged and run.