Font Size: a A A

Research And Development Of High-speed Inspection Image Acquisition And Processing System Based On Layered Architecture

Posted on:2015-07-09Degree:MasterType:Thesis
Country:ChinaCandidate:J ZhangFull Text:PDF
GTID:2298330431983052Subject:Pattern Recognition and Intelligent Systems
Abstract/Summary:PDF Full Text Request
With the continuous development of image processing technology and integrated circuit technology, digital image of the high speed processing demand is higher and higher. The application of image real-time processing in the inspection image has solved the problems and difficulties existing in the inspection. Therefore, the real time processing of digital image becomes a research of the difficulty and hotspot. Large amount of image data and real-time image processing belong to computationally intensive operations. The FPGA (Field-Programmable Gate Array) of the characteristics of parallel data processing is very suitable for some real-time and pixel level image processing. Common digital image collection and processing system first uses the image sampling system to generate the visible image file, and then calls the packaged function to process the generated image under the operating system, such as Windows operating systems and so on. This leads to the slowly image processing and it is difficult to meet the real-time requirements of image processing. Inspection image high-speed data acquisition processing system designed by this thesis, can complete inspection image acquisition and real-time processing.Paper first put forward the inspection image acquisition system’s overall architecture, mainly including CMOS image acquisition module which using1/2inch1.3million pixels sensor MT9T001, SDRAM image storage module using HY57V283220T capacity of128Mbits, FPGA image processing module using Altera company Cyclone series III EP3C16F484C8and VGA video display module. Then detailed introduce various modules and the specific working process of the system hardware structure and the hardware language processing process. The FPGA use I2C protocol to driver CMOS sensors to collect images and use image interpolation algorithm to convert image to RGB format of30bits, the cache part using two pieces of SDRAM as caching, the processed image shows through the VGA interface on an external monitor after process by hardware structure.System can complete the whole process including image acquisition, storage, processing and display. System works stability, occupies system resources reasonable, meet the real-time requirements of image processing, image display clearly.
Keywords/Search Tags:Inspection of image acquisition and real-time processing, FPGA, CMOSsensor, SDRAM, VGA
PDF Full Text Request
Related items