The Design Of A High-speed Data Acquisition/playback System Based On FPGA

The technology of digital intermediate frequency is becoming important technologies in the modern radar reception and signal processing because of its stability, reliability and high flexibility. It's one of the important technologies to improve modern radar performance, and will be certain trend of the radar receiver development. The relative high-speed data acquisition system plays a very important role in whether simulation is demonstrated formerly or result is validated and arithmetic is improved later. So, in the design of modern radar system, we are exigent to design a high-speed radar acquisition and playback system. It can bring the radar echo signal into computer to be analysed as a part of digital radar reveiver, and also can transfer the radar echo signal in computer to signal processing board for testing.Based on the character of the radar intermediate frequency echo signal and the research achievement before, the paper holds up a scheme of high-speed data acquisition and playback system based on radar intermediate frquency signal, and carries out the design and test of the system. The main function of the system is the realization of radar intermediate frequency signal on high-speed acquisition, high speed transfer, high-speed storage and high-speed playback.The implement of scheme this paper dissertated is based on the initiator burst transfers of PCI interface controller to achive the high-speed data acquisition/playback in the radar. Firstly, the intermediet frequency signal acquired by ADC generates quadrature signals, which is processed by DDC. And, they are transferred to computer to achieve the high-speed data acquisition. The data stored in computer is played back to FPGA with PCI's DMA reads, and transferred to another card for testing by RocketIO of FPGA. The design improves integration and reliability of this system because of the implement of PCI interface controller using IP logicore and the achievement of signal processing & storage in a FPGA.This paper discusses the design of software in the system in detail about driver and application in the last chapter. The driver plays a part of a bridge for application to operate the hardware visually. Finally, this system is debugged and tested. Proved through the experiment, it can achieve 65 MB/s data flow of radar signals' high-speed transmittion.