The Design And Optimization Of The Key Operator Circuit For Orthogonal Frequency Division Multiplexing

With the popularity of high definition television and high definition digital set-top box in daily life,the communication technology for the high-rate and short-distance transmission is more and more important.The standard for 60 GHz High-Rate Wireless Personal Area Network(HR-WPAN)is ratified by the IEEE 802.15 Task Group 3c,the orthogonal frequency division multiplexing(OFDM)is used as the technology of modulation and demodulation for the physical layer(PHY).For meeting the standard,the delay of OFDM is reduced by improving the throughput of the key operator of OFDM.In this thesis,Fast Fourier Transformation(FFT)is proved as the key operator of OFDM by Matlab according to the proportion of the running time.To satisfy the requirement of FFT to support multi-point,the mixed-radix algorithm with radix-4 and radix-8 is used.In order to meet the requirement of the OFDM with high throughput,the 16-parallel FFT is realized by optimizing the read-write scheduling of the input reordering module,and the throughput of proposed FFT is greatly improved due to the four butterfly units operating simultaneously.Based on the design of the FFT accelerator,the first and the most expensive inter-stage data exchanger disappears,which reduces the overall delay of the FFT and improves the throughput.Meanwhile,due to the increase of parallelism,the consumption of hardware resources will increase.To minimize the consumption of hardware resources,the number of complex multipliers is reduced by optimizing the operation time of rotation factor multiplication in the rotation factor module;optimizing the eight conversion modes of read-write commutator and ping-pong buffer to reduce the hardware resources in the output reordering module,where only the N size of buffer is needed to achieve the reordering of the output data.The proposed FFT is synthesized for the Artix-7 XC7A200TFBG484-1 FPGA.The function is simulated and verified by the Vivado and Matlab.According to the comprehensive results,the maximum clock frequency of the optimized MDC-PPFFT structure is 360 MHz,and the throughput rate reaches 2.97GS/s.It meets the requirements of the IEEE 802.15.3c standard,the throughput rate is 14.23% higher than that of the similar parallel pipeline FFT structure.