The Design And Research Of The Reconfigurable Acceleration Platform Based On PCI Express Bus

Technology and Theory of Digital Signal Processing are widely applied in many fields, such as communication, computer and multimedia with the advancement of digital electronic technology. The reconfigurable computing not only has flexibility of microprocessor, but also has high performance of application specific integrated circuit. Some application algorithms can be accelerated by take advantage of the excellence of reconfigurable computing. The technology of PCI Express bus has been widely used in many applications. It is suitable for reconfigurable computing with its high performance, outstanding reliability. The development of FPGA also provided hardware platform for reconfigurable computing in recent years.Firstly, different coupling manners are analyzed deeply in this thesis, and then the development of IO Bus in computer system is investigated. According to these, a kind of reconfigurable acceleration platform based on PCI Express Bus is presented; in order to satisfy the bandwidth of data transfer, the Hardware Interface Unit(HIU) is designed, which is accorded with the standards of PCI Express; it has high practical value to speed up Fast Fourier Transform (FFT), which is the core technique of DSP. So Accelerate Function Unit (AFU) is designed to implementation FFT processor with single. Finally, AFU and the whole platform are simulated and verified. The experiment results show that this reconfigurable acceleration platform speeds up FFT computing well.