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The Architecture Design And Hardware Implementation Of An IPTV STB

Posted on:2008-12-14Degree:MasterType:Thesis
Country:ChinaCandidate:H Q ChenFull Text:PDF
GTID:2178360272468942Subject:Physical Electronics
Abstract/Summary:PDF Full Text Request
Ethernet passive optical networks (EPON) are emerging access network technology that provides a low-cost method of deploying optical access lines between a carrier's central office and a customer site. IPTV over EPON transmission system is designed in our project, which can provide multimedia traffics to customers. Triple play will become true and FTTH will be also grounded.Key technologies in this system are introduced, which include EPON, multimedia encoding technology. System structure and working flow is described in detail, including technology scheme of each part. According to DVB-C, digital TV signal is received. TS streams are demultiplexed and decrypt. IP stream is made up of TS streams and transmitted in EPON. STB which is at the client end receives Ethernet data, and gets the MPEG-2 TS through network processing. After that, STB parses TS file, decodes video and audio, analyzes SI data, and sends the gained data to TV to display video and EPG. Besides, STB fulfills the web browser.Technical requirements and main scheme of an IPTV STB are analyzed. It's based on AMD Au1200 processor with Linux operation system. The hardware and software architectures are introduced, together with functional description of every part.The hardware development process is also presented in details in this article. The main modules of IPTV STB, such as power and reset module, clock module, memory module, video/audio processing module and network processing module are explained. The inner structures of Au1200 with MIPS core are introduced. Mean while, the system debugging process are described. The hardware errors and their causes and solutions were analyzed.The paper also describes in detail the Implementation of the Bootloader and the modification made for the IPTB STB. The FPGA hardware design, code Implementation and code are analyzed in detailed. The Signal-Tap II logic analyzer implementations based on FPGA are described. Meanwhile, the paper also describes the solution for PCB design to avoid SI/EMC problems.Finally, the STB test result and system integration method are presented.
Keywords/Search Tags:EPON, IPTV, STB, SI
PDF Full Text Request
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