Memory Arrangement Optimization And Multitask Scheduling Of MPEG-4 CODEC

DSP (Digital Signal Processor) is well on the way to be more and more widely used in video processing and the embedded video CODEC (enCOder/DECoder) based on DSP is one hot spot in research and applications. The characteristics of DSP architecture, such as eight functional units, enhanced Harvard architecture, limited storage, and speed gab between on-chip access and off-chip access, are the challenges of video coding and decoding. According to the characteristics of DSP architecture and RTOS (Real-Time Operation System), a MPEG-4 CODEC is designed and optimized to meet the real-time demand, minimize the storage and power, and enhance adaptive capability.The VLC (Variable Length Coding) code table consumes much storage resource, and VLC is becoming the choke point of video coding on DSP because of its serial characteristic. So the VLC is improved by reorganizing the VLC code table from the point of view of memory arrangement. Intra VLC table and inter VLC table are both indirect-indexed. Also the strategy of frame form, buffer control and multichannel receive based on multitask scheduling is studied and implemented in order to solve the problem of data error and data-arrive jittering and to make sure the CODEC can fetch data simultaneously from different sources, which have different IP addresses.The size of the reorganized VLC tables is 1.25% of the old table and it can be put into the on-chip memory. The DSP CPU load can be 12% ~ 75% to adapt for different decoder's load through adjusting the parameter when decoding 4-channel compressed CIF video stream at 500bps. Also the right point that make the std of CPU load approximately smallest can be found, and that is the approximately optimal point of decoder stabilization.