Hardware Design And Implementation Of VLD And IQIT In AVS Video Decoder

Audio Video coding Standard(AVS), independently developed and owned by China, is a fundamental standard in digital TV, IPTV and other audio/video based systems. AVS Part2, the video part, defines the highly efficient second generation video coding technology. Its implementation is simple and easy. Moreover, it has coding performance close to H.264. Although the coding efficiency of the AVS is better than previous standards, for some real-time applications, the complicated computational characteristics lead great challenges for today's VLSI implementation.Based on analysis of Advanced Coding of Audio and Video Standard deeply, especially variable length decoding, inverse scan, inverse quantization and inverse transformation, this paper introduces the design of variable length decoder, and inverse quantization and inverse transformation. Variable length decoder uses the Barrel-Shifters and optimizes the look-up table index to meet a higher speed and a lower overhead and also reuses some modules in order to reduce the cost of hardware. Inverse quantization and two ping-pong RAM in inverse scanning module together save the processing time. A novel pipeline structure of the 1-D inverse transformation implementing way introduced in this paper is extremely low-cost and high-speed.In whole design, the Top-down design method is used. The design is described in Verilog HDL and a software reference model is made based on RM52j. According to Advanced Verification Methodology, testbench is constructed to functionally verify the design by using SystemVerilog, which uses transaction-level strategy, constraint-random and coverage driven methodology. The testbench improves the verification efficiency and reusability. Function simulation has been completed on each module by using ModelSim. Based on appropriate strategy of synthesis and method of optimization, three modules are synthesize by using SMIC 0.18μm CMOS technology library.The verification and simulation results all indicate that the design of the three modules has achieved requirement.