Data Memory Arrangement In ASIC Design Of Video Encoder

Video Coding technologies are widely used in different applications such as digital TV broadcast and multimedia communication, which save the bandwidth and minimize the amount of storage. A single chip of video coding provides a feasible solution for real time video application. The digital circuit is mainly composed of logic and memory unit. It's necessary to optimize memory unit not only in individual modules but also in the whole system. It's important to consider memory design combined with the pipeline, bus bandwidth, the architecture of modules and throughput and so on.The hybrid video coding architecture is introduced in the paper first of all, followed by the flow chart of application-specified-integrated-circuit (ASIC) design, the bus interconnection specifications, and the development of video coding technologies both domestically and abroad. Then the content of data memory organization in ASIC design of video coder is specified.Memory design falls into two parts as external memory design and on-chip memory design from the system perspective. After the feature of SDRAM widely used external memory is analyzed, memory organization of pixel information and control information is present based on multiple banks architecture of SDRAM, in order to minimize access latency and save the bus bandwidth. The algorithm of frame buffer control for multiple reference frames is present as well as the hardware architecture, which is able to skip frames, insert I picture and insert random access point and so on.Pipeline of the hardware modules and external memory access are involved in on-chip memory design. The data for different modules are buffered due to different pipeline stages of the modules. Different data rate matching is discussed in the example of the FIFO design of video capture module. Data reuse in dual port RAM is discussed in the example of the hardware design of interpolation data organization module.Memory unit is considered with throughput and logic area in individual modules. Two hardware architecture of deblocking filter for SD and HD application separately is presented, which meets the constraint of the working frequency and achieve the high throughput without logic and memory area significantly increase, based on modified deblocking order and local memory access optimization.Memory organization for HD application is discussed on the basis of the bandwidth requirement. The conclusion for pictures with different resolutions in external memory is drawn in the end.