Video Playback In Mpeg Decoder Chip Design Research And Implementation

As an International standard, MPEG finds its wide applications in HDTV, multimedia technology and DAB. Aiming at designing of an video display system in the HDTV source decoder based on the MPEG, this paper conducts an in-depth research of video display algorithm and its standard, and designs two main subsystems : Video Post-Processing System and Digital Video Encoder.In the design of Video Post-Processing System, this paper presents a minimal resource architecture, which achieves all the video format conversions but uses minimum operation units and storage. After reviewing many classical image interpolation methods the paper proposes a image interpolating algorithm based on edge and get a high image quality.In the design of Digital Video Encoder, the paper presents a lot of optimization methods on arithmetic and resource. By observing the the flow of processing in Digital Video Encoder, this paper takes advantage of the linear system to remove, optimize, reuse and merge the data processing units, which reduces the resource by sacrificing some performance. By simplifying the process of filters and look-up-tables, the storage and operation units are cut by 1/8 and 1/2, respectively. This paper points out the shortcomings of the video performance, designs two arithmetics to compensate the nonlinear of DAC and DDS accuracy, which improves the video performance.After accomplishing the arithmetic design, this paper presents the development of chip. The result goes through the simulation, FPGA validation, MPW and NRE chip test, proved to meet the "broadcast quality" target specifications. Comparing to other chips with same performance, the design of this paper has smaller area.