The Design And Implementation Of High Performance DSP Level-One Data Cache Controller

DSP(Digital Signal Processor) is a kind of processor for digital signal processing, which is the key of digital signal processing system. DSP has been developed fast and applied widely after being invented. It is applied widely in many fields, such as communication, military and household appliances. The organization of on-chip memory system affects DSP's performance a lot. So the memory sub-system becomes more and more important. The Cache technology is one of the valid methods to solve this problem.YHFT-DX DSP is a 32-bit fixed-point high performance DSP being designed by NUDT. Its architecture is very long instruction word (VLIW) and can issue 8 instructions in a cycle. Its CPU will run at the frequency of 600MHz and deliver 4800 MIPS. The author has taken part in the design of YHFT-DX DSP, and was mainly responsible for the designing, implementation and verification of level-one data cache controller.The research work of this dissertation mainly includes as follows.This thesis analyses the YHFT-DX DSP architecture and two-level memory structures, and does some research on the modern cache design techniques. For the characteristics of YHFT-DX DSP,the access technology of misaligned memory based on separate-memory controlling is designed.The designing and implementation of the L1D are completed. Five Station pipeline is designed to achieve efficient operation of Load and Store, and the Store operation only required to be completed on the first three cycles. Some technologies are achieved excellently, such as the separate-memory control, transmission mode and misaligned memory access at each station of pipeline operation. Using of snoop mechanism safeguards the consistency of lower memory.The functional verification from the module to the system-level of L1D is finished. A feature-rich test code is developed so that all cases of the Load and Store instructions can run correctly. And the typical algorithms program runs in chip-level, such as MPEG-4, H.264 and so on, and analyze from the coverage.The L1D is synthesized and optimized. It analyzes the critical path after synthesizing, using multi–optimization strategies such as adjusting logic structure, balancing stage logic structure, full custom and semi-custom combinative design, and eventually eliminating the critical path, so that the design of L1D achieves the entire goal. After optimization, the total delay of the netlist is no more than 1.26ns in the typical condition with the 0.13um process and the goal of the design is met.