The Design Of Encode And Decode Circuits In PCIE Interface Chip

PCIE(PCI Express) is the third generation high performance I/O bus used to interconnect peripheral devices in applications such as computing and communication platforms.The prominent character of PCIE is that high speed data transmission can be realized by dividing into lanes.Physical Layer supports×1,×2,×4,×8,×12,×16 and×32 lanes bandwidth.Bandwidth 2.5Gb/s can be provided by each lane in each direction,and bandwidth times with lane times.At present bandwidth can reach 10Gb/s,and it has big potential for development.This thesis realizes the design of 8b/10b encode and decode circuits in Physical Layer in PCIE interface chip using the representative ASIC design flow.The design includes function definition,RTL realization,function simulation,logic synthesis and place&route.This study analyses encode and decode process in PCIE specification at first,and then divides the whole circuit into some modules,describes the function of each module using Verilog HDL,and achieves RTL level realization.Make the RTL level simulation using VCS tool.The simulation result is consistent with 8b/10b encode table result,thus,the RTL code correctness is validated.Design Compiler tool converts RTL level code into Gate level netlist,and the synthesis library is smic 0.18μm library.Make the Gate level netlist simulation with the clock period 7.5ns namely the frequency 133MHz,and the sdf file and smic library is need in this simulation.This simulation result is the same as the result before synthesis,thus,the Gate level netlist correctness and clock frequency 133MHz are validated.Astro tool converts Gate level netlist into layout with smic 0.181am 6 layers metal library.The layout passes the DRC and LVS checks and meets timing request.The study results including Verilog code,simulation waveform,logic diagram,and layout are given at last.