The ASIC Design Of Remote Control Encoder And Decoder

Multifunctional remote control encoder chip, MT-5 and decoder chip, MR-5, hav-ing the address code study ability, can be applied in remote process and long-distancedata transmission of multiple equipment in civilian and military domain widely. Theencoder chip can transmit address code study request signal to the decoder chip, thedecoder chip firstly identifies the request state and detects other data after receivingthe request signal, then studies the address code. When the study completed, the con-trol functional request signal is transmitted from the encoder chip to the decoder chip.The decoder chip then identifies the request state, judges the address code, detectsother data and drives relevant control function.Digital circuit is the main part of the remote control encoder chip and decoder chipdesign in this thesis, containing minor amounts of analog circuit. The whole design isdivided into two parts, the front-end design and the back-end design. According to therequest of the chips'functional and electrical parameter, the method of top-to-down isadopted in the front-end design, functional module division and behavioral descriptionand function simulation and verification are firstly carried out in the Quartus II, thenthe method of whole schematic composer is adopted to design the specific circuit andcarry out the T-Spice simulation of every function in the Tanner circumstance, puttingforward multiple circuit structures which are artfully designed, retrenching the circuitscale, optimizing the circuit performance. The design scheme's feasibility of front-endcircuit is testified through the FPGA hardware verification at the end. The back-enddesign is completed in the Tanner L-edit software, and the related process file and DRCand LVS inspection file are compiled according to the process document and the designrule document strictly.The unit layout gallery needed by the chip is optimum designedby using the full-custom method, finishing the encoder chip and the decoder chip'layout gallery design by using the unit layout gallery finally. The unit layout galleryand the two chip'layout gallery both past the physical verification. In ordering toreduce the scale of chips'layout gallery , the manual placement and routing method isadopted to accomplish the layout gallery design, optimizing the area and performanceof the layout gallery to the utmost extend.The N well 5V,0.5μm silicon gate technology and the two-layer metal wiring areadopted in this pair chip, having the characteristics of low cost and mature processand stable performance, laying a foundation for the chip's favorable market prospects.