| With the continuous development of the wireless communication industry,WIFI and Bluetooth have become a must-have for wireless communication chip manufacturers.At the same time,in order to meet the further needs of high bandwidth and high-speed information transmission,Ultra Wide Band(UWB)technology has emerged in recent years and has become one of the research hotspots in this field.Regardless of the kinds wireless communication technology,the important technical core issue is to ensure the accuracy of data during wireless transmission.This article conducts research based on UWB communication,using wireless channel coding technology to achieve bit error rate control and data error correction.This article first introduces the main content of UWB protocol and the advantages and disadvantages of UWB communication compared to current mainstream wireless protocols.It also introduces the communication process of UWB wireless communication,including the sending circuit workflow,receiving circuit workflow,and data format.Secondly,this design provides a detailed description of the module design objectives,design ideas,specific operational processes of each module,and specific implementation logic.Mainly based on the HRP UWB PHY protocol in IEEE802.15.4A(IEEE Standard for Low Rate Wireless Networks),a wireless channel encoding and decoding module was designed using Verilog HDL.The encoding method specified in the protocol is cascaded encoding using RS(Reed Solomon Encoding)and Systemic Convolutional Encoding.For both encoding methods,there are corresponding decoders that correct errors and restore the encoded content to obtain the original data before encoding.This design specifically includes four modules: the RS encoding module for the transmitter(TX)and the convolutional encoding module;The Viterbi decoding module and RS decoding module used for the RX implement the circuit design logic of the whole channel coding and decoding physical layer through several relatively independent functional sub modules within the four main modules according to the modular design thinking.finally,after completing the RTL code of all modules and passing module level simulation,it is integrated into the entire system for pre simulation verification of the entire chip’s transceiver function level.After the completion of the whole pre simulation Functional verification,the DC comprehensive verification of the static timing,power consumption assessment,and gate level netlist is performed based on the UMC40 nm process and the 125 MHz clock.After STA and the post simulation performed at the 125 MHz clock frequency,The time constraint is confirmed.After the entire chip simulation process is passed,it is confirmed that the design is correct and the performance meets the standard. |
