Development Of Arc-Compatible RISC IP Core

Now, the design and manufacture technology of VLSI have been perfected. A great progress has been made in the design of MPU, especially embed MPU. The research and development of RISC CPU, is vital for the development of SOC (System On a Chip).It becomes the necessity direction to develope the configurability and extensibility of embed MPU to be configurated and extended by user or developer thereby get specifical speed, power and characteristics, and obtain the optimization of application efficiency.Firstly, the thesis briefly introduced the purpose and significance, summarized the development and characteristic of embed MPU especially RISC, and illuminated the develop survey of extensible and configurable MPU.Afterwards, the thesis discussed the whole design of ARC 600 MPU, briefly introduced all kinds of features of the MPU, described its configurability and extensibility, and presented the 32bits/16bits instruction set.And then the structure was designed, the modules were partitioned, and the architecture diagram was given. After that the thesis introduced the partition and configurations of register set, described the functions of chief function modules including five stage pipeline, instruction fetcher, instruction aligner, LD/ST unit, host interface and interruption unit,and discussed the design details.After the success of system design, an automatization test bench is built according to the complicacy of SOC verification and the importance of systemic test bench , and the buildup of the test bench were described also. The thesis then finished RTL level simulation in this test bench and presented the verification results. Finally, the logic synthesis was finished using Design Compiler. The thesis particularly introduced synthesis setup and optional configure according to the configurability, and illuminated the synthesis flow including design restriction and optimize restriction.The synthesis results were definitely correct in terms of the following static timing analysis and format verification.