Design And FPGA Verification Of An EOS Chip

With the rapid development of Internet and the further extension of broadband access networks, data traffic has become one of the dominant traffic types in telecommunication market in recent years. Unlucky, the pure IP network with huge constructive costs can not meet the public telecommunication service requirements. Emerging EOS (Ethernet over SDH) technology is capable of handling various data traffic on SDH network efficiently, and furthest saves the existing network resources.A feasible and effective integrated EOS facility solution, with its FPGA physical verification, is proposed in this thesis. Firstly, features of EOS and key technologies involved in EOS chip are described in detail. Secondly a general design scheme of the EOS chip is presented, including the function definition and module partition. Then the design scheme and dynamic simulation with timing for lOOMbps Ethernet traffic mapping/demapping section and 1000Mbps Ethernet traffic mapping/demapping section are discussed respectively. Finally, the FPGA implementation, board-level debugging and testing of this EOS chip are presented. The test results indicate that this EOS chip is capable of providing simultaneous transmission ability of data traffic and voice traffic over SDH and performance monitoring ability.The Top-Down design methodology and RTL-level Verilog HDL are adopted in this thesis. Based on Xilinx ISE 9.1i integrated environment, functional simulation, logic synthesis, staic timing analysis, dynamic timing simulation with timing and FPGA programming of the design are completed. Use Mentor Graphics Modelsim to perform functional simulation and dynamic simulation with timing, similarly, use Synplicity Synplify Pro 8.1 to perform logic synthesis and staic timing analysis. Considering the design scale, performance and price of diversified FPGA devices, Xilinx Spartan-3E series FPGA device XC3S500E-4FG320C is chosen for implementation of the whole design. After downloading the created programming file into FPGA E~2PROM, the EOS chip is debugged in Xilinx Spartan-3E Starter Kit board environment, the performance testing of this EOS chip is carried through then.The main merits of this thesis are as follows: A feasible design scheme of Ethernet over SDH chip is submitted in detail. A good many of difficulties in EOS chip design, such as parallel scrambler, parallel descrambler, GFP encapsulating and decapsulating circuit, superblock generation and interpretation circuit are designed and implemented owing to the author's own battle. Additionally, two types of board-level debugging method are put forward in this thesis.