The Implementation Of Channel Codec For Digital Video

With the guradual acceleration of the digitalization, the demands of Digital Video and Digital Image increase continuously, Digital TV Broadcast and Mobile TV develop rapidly, which all require more strict demand for the quality of digital video and image. However, in the course of the data transmission, the image quality inevitably decrease, sometimes even cannot play due to the worse performance of transmit media as well as the incoming noise interference. As a result, we need Error-Correct-Coding (also called Channel-Coding) which can decrease the error code as many as possible to insure the image quality during the transmission. In the Digital Video Broadcast (DVB) system, we make use of Channel Coding in all kinds of media, no matter Satellite, Cable, or Terrestrial Broadcast.According to the standard of DVB-T, the design and the hardware implementation of the Channel-Coding system for digital video transmission based on the key technology of Channel Coding in DVB standard is discussed in this thesis. In the system, the channel Codec and Source is connected with a module of bidirection convertion between the Asynchronous Serial Interface (ASI) and Synchronous Parallel Interface (SPI) of video transmission interface for MPEG-2. The module make the system have the simply processing, highly expandability of SPI and the few wires, long distance transmission performance of ASI; also the system uses G703 standard on Channel interface. The interface of G.703 has the feature that makes directly connection among digital communication devices, which giving a comparatively large flexibility in choosing the type of Channel.Basing on the deeply understanding of RS encode/decode algorithm, interleave/deinterleave algorithm, convolution coding/Viterbi Decoding algorithm, this paper gives a design solution for the whole channel which has been implemented with Spartan III series chips of Xilinx Company. Before the RS encoding, there is a module named "rate control" to match the rate of data-in and data-out so as to meet the special challenge for data transmission rate according to the G703 spce. In RS decoding process, Pipeline mechanism is introduced to enhance decoding efficiency. RAM recycling division is applied in both interleave and de-interleave, using RAM addressing I/O operation to implement convolution interleaver/de-interleaver. This approach has the feature that easy circuit, fast implement, little cost. VITERBI decoder use truncate decoding which increases the decoding efficiency with little influence on decoding accuracy.