Designs Of ALU And CP0 Blocks Based On MIPS32

Recently, the open-copyright MIPS architecture CPU become welcome. The Router of Cisco,the colour network printer of IBM,the 4000,5000,8000,9000 series laser printer and scanner of HP,the Playstation and Playstation2 of Sony etc. all are the products of MIPS microprocessor which used different MIPS instruction set.The Arithmetic Logical Unit (ALU) of MIPS CPU integrated all kinds of arithmetic function and logical function unit, they are add, subtract, multiply, divide, Boolean calculation and shift operation etc.Coprocessor CP0 is the interface between MIPS instruction set and peculiar source structure.CP0 gives the complete control of CPU state and operation mode.By studying the MIPS 32 instruction set,arithmetic of fixed point ALU and structure of CP0,this paper designed the ALU and CP0 blocks with verilog HDL.After function simulation,I did the logic synthesis and the timing simulation for the netlist of logic synthesis.The simulation results indicates that the design accord with the specification.By far, the design is used as a part of CPU core of one company's SOC project and passed the FPGA validation.Because of the whole plan of the project,we intend to tape out in April.