A novel floating point arithmetic coprocessor

In this dissertation, we develop a novel high speed Arithmetic synthesizable Coprocessor capable of implement the following operations: Addition/subtraction, Multiplication, Division, Square Root, and Inverse Square Root. With area speed tradeoff limitation, our concentration was on designing high speed Arithmetic units with moderate area increase. Thus, we concentrated on developing units that share the same hardware. We developed a high speed arithmetic fused multiply add unit (A*B+C) Capable of addition/subtraction and multiplication. We concentrated on reducing the delay in critical path by identifying the most time consuming operations in the critical path of a basic multiply Add fused unit. We developed a SD high speed fused multiply Add unit. Synthesis tools were used to evaluate our designs and reports showed that the estimated minimum delay of our designed unit was 4.624ns compared to a minimum path delay for the Basic fused multiply Add unit of 112.917ns. This huge increase in speed came at a cost of 8% increase in number of slices in the FPGAs chip and 8% increase in the number 4 input look up tables (LUTs).; Our concentration on the inverse square root, square root, and division (ISD) using digit recurrence algorithms led to the design of a robust unit sharing the same recurrence and same hardware to perform all three operations. Minor differences occur in the initialization stage and number of iterations and final rounding. Other than that all the operation are executed using the same unit. By fusing the unit in this way we also ensure not to increase the area of the complete arithmetic unit. Synthesis tools were used to evaluate our designs and reports showed that our ISD unit has a minimum path delay of 12.443ns. Area was moderate and within range when theoretically comparing three separate units to complete the three operations. We further decrease the latency of the ISD unit by implementing short fast adder in the critical path.