The Design And The FPGA Implementation Of RS Decoder Based On ME Algorithm

RS code has been widely used in communication systems, digital television and computer storage systems to enhance the reliability of data transmission. This paper takes the RS (204,188) decoder which is defined in DVB standard for a research. It introduces the Modified Euclidean (ME) algorithm and the design and implementation of the RS decoder which is based on this algorithm in detail. Also the decoder uses the pipeline structure for the design. And we make analyze and model of every module of the decoder. Through the EDA instruments we complete the verification of logic function of the design and the synthesis of the designed circuit. At last we implement the design in the FPGA to finish the title Top-Down design of the decoder.The main tasks of this paper contain: 1) Use a more highly effective ME algorithm, which not only reduce the amount of the logic unit, but also improve the speed of the circuit. 2) Use the Verilog HDL to realize the circuits of RS decoder, which include the steps of designing the circuits of multiplication and division in finite field, the key equation solution circuit and so on. 3) Modify the Chien search circuit to simplify the structure of circuit.4) Implement the RS decoder by using the FPGA chip named EPIC20F324C8 of Cyclone series in the Altera company.After the synthesis and the implementation of the decoder, we get the result that the scale of this RS (204,188) decoder is approximately 35 thousand gates and the operation frequency is about 134MHz.