The ASIC Design Of 300MHz High Performance Direct Digital Systhesizer

A direct digital synthesizer (DDS) provides many significant advantages over the phase-locked-loop (PLL) approaches. Fast settling time, sub-Hertz frequency resolution, continuous-phase switching response and low phase noise are features easily obtainable in the DDS systems. Since having the outstanding performance, the DDS systems are used widely in fields such as signal generator, the modulator in the base station, medical imagery, phase-controlled radar, communication, sonar systems, software radio and so on. Therefore, the research on technology related DDS has become the core techniques in modern technosphere of frequency synthesis.Foreign companies such as Analog Devices and Qualcomm have implemented high performance DDS chip with the operating frequency of 1 GHz, but domestic commercial DDS is in the far future. It is extremely urgent and significant to have independent high-performance DDS with intellectual property. This project studies the relevant theories and key technology of DDS and designs the digital part of the DDS with high performance. Main research and innovation as follows:1. Studies the theory of DDS and summarizes all kinds of algorithms which are commonly used in reducing ROM size.2. Studies the sources of the noise and spurs in the DDS, especially concentrates on the DDS output spectrum impairments that are caused by phase truncation and finite quantization in the sine ROM values, we implement the phase dithered DDS chip with spur reduction techniques.3. Studies the conventional Taylor Series Approximation and proposes a improved Taylor Series linear interpolation algorithm, which reducing the size of ROM nearly 40%, from original 757:1 to 1243:1, while maintaining the same SNR.4. Using Matlab to build the DDS mathematical model to the improved Taylor Series linear interpolation algorithm, and verify the signal-to-noise ratio of DDS output spectral density. Combined the advantages of ModelSim and Matlab, we easily realize the system level verification for Taylor DDS.5. Based on fully studying of improved Taylor linear interpolation algorithm, the digital logic of DDS be designed and implemented using standard 0.18um CMOS process. Four popular working models have been implemented in DDS. Simulations have shown that the new DDS can work at more than 310MHz with the SFDR more than 110dB. The entire digital part of the DDS equivalent to 13K gates and power consumption less than 100mw, meeting the design requirements.