Design And Implementation Of Integrated Services Interface Board Clock Control Circuit

With the development of broad band digital service and diversification of the way used to access to net, access networks has evolved to an integrated net, which can supply the integrated service about access to net, and meeting ability. In this type of net, clock synchronization is the key to keep the data right and system run normally. This paper based on control theory, according to the conception of Phrase Lock Loop and Direct Digital Synthesis, we designed the clock circuit. It realizes the amalgamation of kinds of the ways about clock, which make it has some superiority. In order to guarantee the system to run stably, avoid the huge loss bringing with system fault, we use VHDL language to program CPLD to realize the automatic change between main board and spare board. Further more, we have tested the related clock sign to perfect the design. This design has come into practice, it has certain economy value and theory value.