Study Of Direct Digital Frequency Synthesis And Its Implement Based On FPGA

The fundamental working principle and basic structure of direct digital frequency synthesis is introduced in this paper. On this basis, its ideal spectrum characteristic is induced, analysis of its spurious sources is made and the common methods of restraining spurious are summarized. The research emphasis has been put on the design of accumulator and the ROM table. According to the feature that DDS has a very low refresh rate of input datas, the improved pipeline controlled by "pipeline-timing" signals is used in the 32-bit double accumulator. This structure reduces the number of shift register. In order to improve speed at all levels of pipeline, Carry look-ahead adder is employed in and between groups. Moreover, the spurious improvement circuit is adopted in the phase accumulator to reduce spurious. Based on the symmetry of sine-cosine function and Taylor linear interpolation, a large proportion of compression up to 122:1 is made in the ROM table. 1/2LSB offset is also taken to eliminate the errors, which is produced when the radix-minus-one complement is taken the place of by the complement. The sine-cosine two-way outputs have been achieved in the design.Using the development tools-ModelSim 6.2 and Quartus II7.2 together with hardware description language-Verilog and taking the EP2S60F1020C3 development board as a target device, the development, simulation, synthesis and on-line logic debug of the DDS design are completed. The test results show that it has a max clock frequency of 147.54MHz, max frequency resolution of 0.034226Hz, minimum frequency transition time of 68ns and its dominant frequency is 75dB, when The output frequency is 30MHz. The performance of DDS can meet the design requirements.