Research On The Low Spurious Direct Digital Frequency Synthesis Based On FPGA

Frequency source technology is a technology developed in the70s, which isflexible to use,easy to controland has superior performance. With the development of3G,4G communication and new system radar, short time of frequency conversion, highfrequency resolution, continuous phase of DDS (direct digital frequency synthesizer)are increasingly becoming the key factor of the systems. DDS at present has beenwidely used in missile, electronic information, communication, phased array radar andthe SAR.This thesis focuses on direct digital frequency synthesizer (DDS) as the researchobject, at the same time, according to the problems and challenges encountered inmodern chip test, the direct digital frequency synthesizer (DDS) and measurabilityalgorithm will be researched and designed for implementation. DDS needs to meet thespecific testability(DFT: the Design For Testability) requirements. There will be twotest algorithms embedded in the DDS. Main content is:1. Study and analysis of direct digital frequency synthesis technology. In order tofacilitate research and design of DDS, this article builts a GUI simulator based onmaltlab. The simulator can simulate phase truncation and amplitude quantization, theinfluence of the phase jitter technology to the DDS signal. It uses powerful plot functionof matlab, which can intuitivly show frequency spectrum and time sequence diagram.2. According to the specific requirements of the DDS chip, this paper puts forwarda new design method. The design of accumulator is in the manner of pipeline.At thesame time, in order to increase the compression ratio of the ROM look-up table, AngleDecomposition method is used to compress the size of the ROM.these mehods improvethe circuit frequency and data throughput and reduces the power consumption of theROM.3. In-depth study for embedded SRAM’s built-in self-test method, according to thecharacteristics of the DDS, a March C+extension word is used. To complete in testingthe word failure and improve fault coverage, the test vector data background will beused; As the address sequence of the March C+algorithm is not strict, LFSR is used to replace traditional counter.4. Research on the JTAG boundary scan algorithm and design it. The chip cancomplete board level system test. The thesis puts forward a new test structure, whichcombines MBIST and JTAG design together. In order to reduce the chip pins, it usesthe JTAG to control the MBIST.