Research And FPGA Implementation Of BCH Encoder And Decoder In Digital Television Broadcasting System

Television program digitization is a significant transformation during the development of broadcast television industry, which is honored as a strategic technology of the new century. Digital television broadcasting system, the third generation mobile communication system and the next generation Internet, constituted three major information infrastructure of the 21st century. Digital television broadcast standard will profoundly influence the development of the information service industry, the development of transmission/reception terminal manufacturing industry,etc. Meanwhile, digital television will gradually integrate other techniques of the communication and information field so as to form a completely new and huge digital television industry. The development of digital television chip will have a significant effect on the enhancement of our technical power, and even our national strength.Error will occur during the transmission since digital television signal is interfered by various channel noises and multi-path effect. For reliable transmission of the digital television signal, technology of channel encoding has been widely used in digital television broadcasting system. BCH/RS has been employed in many digital systems' standard because they provide powerful function of error correction.. Research shows that iterative soft-decision decoding theory could improve the decoding performance of RS codes obviously. It is important and necessary to do research on suitable soft-decision algorithm of RS codes for digital television broadcasting system.In this thesis we first review the developing status and current situation of digital television broadcasting system and channel encoding theory. Channel encoding blocks in DMB-TH, CMMB and DVB-S2 systems are introduced, based on summary of the application of the channel encoding technology in digital broadcasting systems. Then we make a study on the concatenated codes of BCH/RS+LDPC in the three systems mentioned above and design the hardware platform on FPGA for the channel encoder and decoder of DMB-TH system. We also do research on parallel algorithm for the BCH/RS encoding. Parallel BCH encoder and decoder for DMB-TH system and bit-parallel RS encoder for CMMB system are designed and implemented on FPGA platform. Design of the whole channel encoder and decoder of DMB-TH system have been tested and verified on FPGA platform. In addition, we have done research on soft-decision of RS codes especially on Koetter-Vardy algorithm which is a typical algebraic soft-decision algorithm of RS codes. Finally, we summarize the whole thesis and give a further plan of the research.