On Chip Distributed Operating System Design For NoC Based CMPs

NoC was first proposed as an integral part of System on Chip (SoC) design methodology and architecture. It was designed as the data communication fabric and could be characterized as an ad hoc mixed network.As the number of processors on a single die increasing, the future Chip-Multiprocessors (CMP) will have the same on chip interconnection problem and also require NoC for the same reason as SoC. Usually, CMP has a different software model compared to SoC. Unlike the design time specified SoC systems, CMP is more likely to be used as general purpose processors. And a general purpose operating system is required for NoC based CMP.The hardware difficult for developing a general purpose operating system is the main memory bottleneck problem, each on chip processor may raise main memory references respectively, and the main memory becomes a critical resource for processors. If the problem is not well solved, the communication between chip and memory must be established via specialized IPs, which is SoC way, and a general purpose operating system cannot be build. Therefore, we first introduce Network Main Memory (NMM) to eliminate the bottleneck problem.In this paper, we analyze the properties of NoC and NMM, and claim that there should be an on chip distributed general purpose operating system for NoC. We first propose the principles of on chip distributed operating system. According to the principles, we develop our design of on chip distributed operating system, including IPC, Memory Management, Scheduler, Kernel Service and Device Management.At last, experiments are carried out to show that, the multiple communication channels of NMM are necessary, and doubling the number of the channels will have memory reference latency reduced to 18%-46%. And the on chip memory is advance to main memory for communication of processes with the latency reduced to 33%-50%.Therefore, NMM and the on chip operating system we proposed are good approach to attack the memory bottleneck problem and can make most efficient use of NoC chips.