The Design Of Divider Unit In High Performance CPU

Arithmetic computation is a key function of Central Processor Unit (CPU). Among basic arithmetic operation, division is the most difficult one to implement. Therefore the design of dedicate hardware divider is usually the vital part in CPU development. Since the design of an embedded CPU is more concerned about cost reduction, its ALU design usually emphasizes on flexibility rather than performance. This orientation demands solutions that consume minimum die area. This dissertation describes the design and implementation of two types of integer dividers. The first one is a low-cost radix-2 divider based on a 64-bit standard adder and minimum complementary logic. The second one improves performance remarkably by employing Redundant Number System (RNS). This algorithm enables the realization of a radix-4 divider through two cascaded radix-2 RNS kernel. Comparing to a traditional radix-4 SRT divider based on large storage array, this design significantly reduces the hardware structure complexity without performance loss. Using a radix-4 SRT divider design as a reference, chapter 4 compares three different designs in terms of algorithmetic efficiency and timing delay. Efficient IC back end design methodology, which ensures chip performance, is discussed along with the dividers.