The Design And Implementation Of Divider Unit Based On FPGA

According to the project's needs and future development needs, This design has completed division operation of 32 bit integer and the single precision floating point with divider design theory and practice of new progress. Throughout the design process,First, The existing division algorithm was analyzed, Then select Digit Recurrence Algorithm design as the core algorithm. The paper detailed analysis of the selection function,which includes radix choice,the expression of quotient and On the Fly conversion.The design not only use Digit Recurrence Algorithm, but another algorithm is used to contrast from speed and hardware area.Digit Recurrence algorithm has been made improved, remainder Compared with the constant rather than the divisorand. quotient uses the redundancy expression, so large umber of comparators can ba discarded. This improvement greatly reduced the time delay of business selection functions which in the the critical path. The result shows that the 32 bit integer operating frequency is 73MHZ and The single precision floating point division can be accurate to six decimal places.For the same algorithm, The design has used radix 2 algorithm and radix 4 algorithm to realize. Theory and simulation results indicated that radix 4 algorithm had an advantage in speed than radix 2 algorithm, but radix 2 algorithm used less hardware resource than radix 4 algorithm. Therefore, A conclusion can be summarized that speed and area are mutually restrict . According to the different practical application, choosing the different algorithm.