Modeling And Hardware Design Of The Computing Unit

In recent years,artificial intelligence technology used widely in image recognition and speech recognition.People's demand for processor performance is also increasing.Due to the limitations of von Neumann's structure,the computing performance of traditional CPUs and other processors is gradually unable to meet the computer performance requirements of artificial intelligence solutions.Biological neurology has a high efficiency in processing energy consumption.Drawing on the biological neural system to modify and improve artificial neurons and networks has gradually become a new direction for the development of artificial intelligence.At the same time,the neurons in the deep neural network only have the calculation function and lose the neural characteristics of the biological neuron,which also affects the overall performance of the neural network.Given the current problems of artificial neural networks,the thesis simplified the mathematical model of biological neurons from the perspective of biological neural information transmission and tried to model the basic neural unit hardware.Inspired by the neuron compartment model,Izhikevich single-compartment neuron model with high computational efficiency and more neural computing characteristics was selected as the basis of the neural unit in the design of the basic neural unit model.In this paper,a new design and implementation of the model from the perspective of bionics are carried out,which makes it deviate from the mainstream implementation and achieves all the neural computing characteristics of the model while improving the work efficiency.In the structural design of the basic neuron unit and the rich achievements made in biological neurology,the biological neuron information transmission process is mainly composed of four parts:external information conversion,electrical signal transmission,information update,and weight update of the neuron connection.Therefore,the core modules of the basic neural unit are divided into the event generation module,stimulus generation and classification module,threshold voltage update module,membrane potential update and spike generation module.The first module converts the information of external neurons into events and classifies the attributes.The second module mainly convert events into stimulus,and at the same time classifies them according to the current input forms at different moments.The third module update the voltage of the basic neural unit in different neural calculation modes.The last module is mainly for the event,input current and threshold value generated by other modules to update the threshold voltage and determine whether emit the spike signals.The parameter controller controls parameter transmission and a weight update module that updates connection weights between basic neural units is designed in the structure of the neuron unit.The hardware implementation uses Verilog language for hardware modelling,and implements these five modules and the parameter controller part respectively.In the simulation test process of the basic neural unit,to ensure the correctness,all the modules were tested in the simulation test initially.After confirming the correctness of the functions of these modules,20 neural computing models of the Izhikevich single-compartment neuron model were simulated one by one to analyze whether the basic neuron functional characteristics in this design were correct.The hardware of the basic neural unit uses design tools of Synopsys to synthesis in the TSMC 65nm process.The total hardware area of the designed in this paper is about 1 594?m2,and the hardware power consumption is about 0.1183mW under the max frequency.Thus,the thesis achieves the expected goal,completes the design of the basic neural unit and its hardware implementation.