Design And Implementation Of FPU In X Microprocessor

X microprocessor is a high performance one in CISC, whose Floating-Point Unit (FPU) has very powerful abilities of processing numerical value. The FPU supports integer, floating-point and packed BCD data formats that the IEEE754-85 standard difines.This paper investigates the architecture characteristic and the method to design high-performance coprocessor and FPU. It present a design of the architecture and the primary datapaths (comprise of exponential datapath and mantissa datapath) and some functional units of FPU in X microprocessor .Then discusses some algorithms of the functional units,especially makes deep researches on division algorithms and square root algorithms. An improved logic structure and a method for implementing the same to perform division and square root operations for radix four division hardware is disclosed and implemented in full-custom on 0.18 micron CMOS technology.A radix four SRT non-restoring division method is employed for the divider, with fixed iteration cycles, the partial remainder in a redundant form comprising a "SUM" and a "CARRY", Carry Save Adder (CSA) iteratively generating a next redundant partial remainder, the quotient in a redundant form comprising a positive quotient and a negative quotient, the two prediction quotient bits being selected from a quotient prediction table, on-the-fly correction and pipeline the components of division steps.A subtractive algorithm for Radix 2 square root is implemented in division hardware without deteriorating the circuit performance for division operation.Models simulation and system instructions verification prove that the implementation is valid and conform to the specification of X microprocessor, and 39 cycles and 70 cycles are needed for division instruction and square root instruction individually.The X microprocessor chip run at 300MHz without any floating division errors.At the end of this thesis, a new improved divider based on radix four division circuit using overlapped quotient bit selection which can produce four bits of quotient per divider cycle is proposed for next generation of higher-performance microprocessor. Theoretically, half of cycles will be saved for this improved structure.