Setting Constraints And Logic Synthesis For Novel PKUnity System-on-Chip

Logic synthesis is aimed to transform the design from Register Transfer Level (RTL) to netlists. It is a crucial bridge between architecture design and physical design. Before logic synthesis, the design constraints should be set properly, inluding timing, area and power constraints. This step is the basis of the sequent work. After that, designers need to accomplish some necessary modification of the design and use a proper flow to carry out logic synthesis. Besides meeting the constraints, the timing correlation between logic synthesis and postlayout should be kept as high as possible. After logic synthesis, it is necessary to check the consistency between its result and the original design. Because of the high integration, complex function and strict constraints, setting constraints and then accomplishing logic synthesis is a crucial work of heavy load.The thesis will firstly introduce the basic theory of design constraints and logic synthesis. Then, taking the novel PKUnity System-on-Chip (SoC) SuperK for example, the thesis will discuss and present the entire RTL flow based on Synopsys Design Compile, from setting constraints to logic synthesis. In order to decrease the timing diversity between logic synthesis and postlayout to improve the correlation, the thesis will present the flows and experiments of logic synthesis with physical constraints. At last, the thesis will discuss checking the function consistency with Synopsys Formality.The experiments in SuperK SoC show that the strategies and flows presented in the thesis can set constraints efficiently and accomplish logic synthesis successfully. Logic synthesis with physical constraints introduced in the thesis can significantly decrease the timing diversity between logic synthesis and the final layout and improve the performance to a certain extent.