Design And Implementation Of The Off-line Logic Synthesis System Based On Iterative Intersection Of Subset Algorithm

The research on the logic indefinite chips decrypting technology is very important for us. It helps our country in importing and adsorbing foreign advanced technology and achieving leapfrog development.The design and exploitation of the off-line decrypting system of the logic indefinite chips is an important approach to analyze the logic indefinite chips. As a main component of the off-line decrypting system of the logic indefinite chips, the processing capacity and efficiency of logic synthesis subsystem has a direct effect on the whole analysis system. With the rapid development of manufacture technique of logic chips, how to accomplish the logical and integrated process of cosmic data initial set rapidly and correctly using the existing computation resources has become a difficult problem in the design of logic synthesis subsystem.This paper addresses the problem of how to improve the processing capacity and efficiency of the logic synthesis subsystem. Based on the thorough research on the logic synthesis theory, The paper analyzes the classical logic synthesis algorithms and the characteristics of chip initial data set during the reverse parsing. Taking the space and time complexity of the algorithm into account, an iterative intersection of subset algorithm is proposed in this paper. And the logic synthesis subsystem is designed and developed based on this algorithm. The test results show that the developed logic synthesis subsystem can accomplish the cosmic data set processing rapidly and efficiently. The processing speed can be further increased through extending the application of this system from single computer to network.