Research And Design Of Extensible FPGA SoC

This paper introduces the design of extensible FPGA SoC based on WISHBONE, which function is easy to be extended.The design is described by Verilog VHL,and also implemented in the Xilinx FPGA chip.On this paper, it first introduces the development of System-on-a-Chip, and also analyses the problems of designing SoC based on FPGA,especially, On-Chip Bus and IP core reuse.It first analyses the extensible problem of SCM application system,and submits a solution based on FPGA.And then it introduces the wireless sensor node and design a extensible SoC based on FPGA,which is under WISHBONE standard.This SoC system makes up of a 8-bit MCU and some peripheral equipment controller IP core.This system can be expand to 16 slaves.Bus-On-a-Chip is the key of interconnecting different IP cores to SoC,also is the foundation of re-use IP core.This paper introduces some common Buses-On-a Chip, especially WISHBONE bus which is a simple, flexible and portalbe system bus.It defines the standard data exchange between IP core modules. It does not attempt to regulate the application specific functions of the IP core.It require few logics and the arbitration methodology is defined by the end user.Variable core interconnection methods support point-to-point, shared bus, crossbarswitch, and switched fabric interconnections.IP core reuse technology is the foundation of designing of SoC.All IP cores in the paper are designed by standard rule and flow,including 8-bit MCU compatible with PIC16C5x,GPIO controller, IIC controller, SPI controller,and UART controller.On this paper,it introduces the design of 8-bit MCU ip core which instruction is compatible with PIC16C5x.After analyzing the instruction and frame,it implement the synchronization between clock and reset signals in the same module.It completes jumping instruction, especially the condition jumping instruction by judging the condition to decide the operation.It instrduces the design of RAM module by Xilinx ISE develop tool,which is support the block RAM of Xilinx FPGA device.In the end,it standard the I/O port by WISHBONE. Finally in this paper,all the IP cores are connect to a SoC with the way of share bus.All the IP cores in the paper,not only single IP core but also SoC,have been synthesised, optimized,static timing analyzer,function simulate,etc.The result indicate all the designs are OK.